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SH7261 Datasheet(PDF) 782 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 782 Page - Renesas Technology Corp |
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782 / 1348 page  Section 17 I 2C Bus Interface 3 (IIC3) Rev. 2.00 Sep. 07, 2007 Page 750 of 1312 REJ09B0320-0200 TDRE TEND ICDRT ICDRS 12 12 34 56 78 9 A R/ W SCL (Master output) SDA (Master output) SDA (Slave output) [5] Write data to ICDRT (third byte) [2] Instruction of start condition issuance [3] Write data to ICDRT (first byte) [4] Write data to ICDRT (second byte) User processing Bit 7 Slave address Address + R/ W Data 1 Data 1 Data 2 Address + R/ W Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 17.5 Master Transmit Mode Operation Timing (1) TDRE TEND ICDRT ICDRS 1 9 2 34 56 78 9 A A/ A [6] Issue stop condition. Clear TEND. [7] Set slave receive mode SCL (Master output) SDA (Master output) SDA (Slave output) Bit 7 Bit 6 Data n Data n Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [5] Write data to ICDRT User processing Figure 17.6 Master Transmit Mode Operation Timing (2) |
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