SH7261 datasheet(778/1348 Pages) RENESAS

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Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 746 of 1312

REJ09B0320-0200

17.3.7

2C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the

empty space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT

to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during

transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF.

ICDRT is initialized to H'FF by a power-on reset or deep standby mode.

R/W

Bit:

Initial value:

R/W:

17.3.8

2C Bus Receive Data Register (ICDRR)

ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR

transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a

receive-only register, therefore the CPU cannot write to this register.

ICDRR is initialized to H'FF by a power-on reset or deep standby mode.

RRRRRRRR

1111111

Bit:

Initial value:

R/W:

17.3.9

2C Bus Shift Register (ICDRS)

ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from

ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from

ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the

CPU.

Bit:

Initial value:

R/W:

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