SH7261 datasheet(775/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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775 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 743 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

RDRF

R/W

Receive Data Register Full

[Clearing conditions]

• When 0 is written in RDRF after reading RDRF = 1

• When ICDRR is read

[Setting condition]

• When a receive data is transferred from ICDRS to

ICDRR

NACKF

R/W

No Acknowledge Detection Flag

[Clearing condition]

• When 0 is written in NACKF after reading NACKF

= 1

[Setting condition]

• When no acknowledge is detected from the receive

device in transmission while the ACKE bit in ICIER

is 1

STOP

R/W

Stop Condition Detection Flag

[Clearing condition]

• When 0 is written in STOP after reading STOP = 1

[Setting conditions]

• In master mode, when a stop condition is detected

after frame transfer

• In slave mode, when the slave address in the first

byte, after detecting start condition, matches the

address set in SAR, and then the stop condition is

detected

SH7261 Datasheet(PDF) 775 Page - Renesas Technology Corp

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