SH7261 datasheet(772/1348 Pages) RENESAS

772 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 740 of 1312

REJ09B0320-0200

17.3.4

2C Bus Interrupt Enable Register (ICIER)

ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and

acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits

received.

ICIER is initialized to H'00 by a power-on reset or deep standby mode.

R/W

Bit:

Initial value:

R/W:

TIE

TEIE

RIE

NAKIE

STIE

ACKE ACKBR ACKBT

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When the TDRE bit in ICSR is set to 1 or 0, this bit

enables or disables the transmit data empty interrupt

(TXI).

0: Transmit data empty interrupt request (TXI) is

disabled.

1: Transmit data empty interrupt request (TXI) is

enabled.

TEIE

R/W

Transmit End Interrupt Enable

Enables or disables the transmit end interrupt (TEI) at

the rising of the ninth clock while the TDRE bit in ICSR

is 1. TEI can be canceled by clearing the TEND bit or

the TEIE bit to 0.

0: Transmit end interrupt request (TEI) is disabled.

1: Transmit end interrupt request (TEI) is enabled.

RIE

R/W

Receive Interrupt Enable

Enables or disables the receive data full interrupt

request (RXI) and the overrun error interrupt request

(ERI) in the clocked synchronous format when receive

data is transferred from ICDRS to ICDRR and the

RDRF bit in ICSR is set to 1. RXI can be canceled by

clearing the RDRF or RIE bit to 0.

0: Receive data full interrupt request (RXI) are disabled.

1: Receive data full interrupt request (RXI) are enabled.

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