SH7261 datasheet(774/1348 Pages) RENESAS

774 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 742 of 1312

REJ09B0320-0200

17.3.5

2C Bus Status Register (ICSR)

ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.

ICSR is initialized to H'00 by a power-on reset or deep standby mode.

Bit:

Initial value:

R/W:

00000000

R/W

TDRE

TEND RDRF NACKF STOP AL/OVE AAS

ADZ

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/W

Transmit Data Register Empty

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When data is written to ICDRT

[Setting conditions]

• When data is transferred from ICDRT to ICDRS and

ICDRT becomes empty

• When TRS is set

• When the start condition (including retransmission)

is issued

• When slave mode is changed from receive mode to

transmit mode

TEND

R/W

Transmit End

[Clearing conditions]

• When 0 is written in TEND after reading TEND = 1

• When data is written to ICDRT

[Setting conditions]

• When the ninth clock of SCL rises with the I2C bus

format while the TDRE flag is 1

• When the final bit of transmit frame is sent with the

clocked synchronous serial format

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