SH7261 datasheet(770/1348 Pages) RENESAS

770 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 738 of 1312

REJ09B0320-0200

17.3.3

2C Bus Mode Register (ICMR)

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred

first, performs master mode wait control, and selects the transfer bit count.

ICMR is initialized to H'38 by a power-on reset or deep standby mode. Bits BC[2:0] are initialized

to H'0 by the IICRST bit in ICCR2.

R/W

Bit:

Initial value:

R/W:

MLS WAIT

—

BCWP

BC[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

MLS

R/W

MSB-First/LSB-First Select

0: MSB-first

1: LSB-first

Set this bit to 0 when the I

2C bus format is used.

WAIT

R/W

Wait Insertion

In master mode with the I

2C bus format, this bit selects

whether to insert a wait after data transfer except the

acknowledge bit. When WAIT is set to 1, after the fall of

the clock for the final data bit, low period is extended for

two transfer clocks. If WAIT is cleared to 0, data and

acknowledge bits are transferred consecutively with no

wait inserted.

The setting of this bit is invalid in slave mode with the

2C bus format or with the clocked synchronous serial

format.

5, 4



All 1

Reserved

These bits are always read as 1. The write value should

always be 1.

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