SH7261 datasheet(766/1348 Pages) RENESAS

766 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 734 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

MST

TRS

R/W

Master/Slave Select

Transmit/Receive Select

In master mode with the I

2C bus format, when

arbitration is lost, MST and TRS are both reset by

hardware, causing a transition to slave receive mode.

Modification of the TRS bit should be made between

transfer frames.

When seven bits after the start condition is issued in

slave receive mode match the slave address set to

SAR and the 8th bit is set to 1, TRS is automatically

set to 1. If an overrun error occurs in master receive

mode with the clocked synchronous serial format, MST

is cleared and the mode changes to slave receive

mode.

Operating modes are described below according to

MST and TRS combination. When clocked

synchronous serial format is selected and MST = 1,

clock is output.

00: Slave receive mode

01: Slave transmit mode

10: Master receive mode

11: Master transmit mode

3 to 0

CKS[3:0]

0000

R/W

Transfer Clock Select

These bits should be set according to the necessary

transfer rate (table 17.3) in master mode.

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