SH7261 datasheet(768/1348 Pages) RENESAS

768 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 736 of 1312

REJ09B0320-0200

17.3.2

2C Bus Control Register 2 (ICCR2)

ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA

pin, monitors the SCL pin, and controls reset in the control part of the I

2C bus.

ICCR2 is initialized to H'7D by a power-on reset or deep standby mode.

R/W

Bit:

Initial value:

R/W:

BBSY

SCP

SDAO SDAOP SCLO

—

IICRST

—

Bit

Bit Name

Initial

Value

R/W

Description

BBSY

R/W

Bus Busy

Enables to confirm whether the I

2C bus is occupied or

released and to issue start/stop conditions in master

mode. With the clocked synchronous serial format, this

bit is always read as 0. With the I

2C bus format, this bit

is set to 1 when the SDA level changes from high to low

under the condition of SCL = high, assuming that the

start condition has been issued. This bit is cleared to 0

when the SDA level changes from low to high under the

condition of SCL = high, assuming that the stop

condition has been issued. Write 1 to BBSY and 0 to

SCP to issue a start condition. Follow this procedure

when also re-transmitting a start condition. Write 0 in

BBSY and 0 in SCP to issue a stop condition.

SCP

R/W

Start/Stop Issue Condition Disable

Controls the issue of start/stop conditions in master

mode. To issue a start condition, write 1 in BBSY and 0

in SCP. A retransmit start condition is issued in the

same way. To issue a stop condition, write 0 in BBSY

and 0 in SCP. This bit is always read as 1. Even if 1 is

written to this bit, the data will not be stored.

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