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SH7261 Datasheet(PDF) 765 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 765 Page - Renesas Technology Corp |
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765 / 1348 page ![]() Section 17 I 2C Bus Interface 3 (IIC3) Rev. 2.00 Sep. 07, 2007 Page 733 of 1312 REJ09B0320-0200 17.3.1 I 2C Bus Control Register 1 (ICCR1) ICCR1 is an 8-bit readable/writable register that enables or disables the I 2C bus interface 3, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. ICCR1 is initialized to H'00 by a power-on reset or deep standby mode. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: ICE RCVD MST TRS CKS[3:0] Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I 2C Bus Interface 3 Enable 0: This module is halted. 1: This bit is enabled for transfer operations. 6 RCVD 0 R/W Reception Disable Enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception |
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