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SH7261 Datasheet(PDF) 762 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 762 Page - Renesas Technology Corp |
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762 / 1348 page  Section 17 I 2C Bus Interface 3 (IIC3) Rev. 2.00 Sep. 07, 2007 Page 730 of 1312 REJ09B0320-0200 Figure 17.1 shows a block diagram of the I 2C bus interface 3. SCL ICCR1 ICCR2 ICMR ICSR ICIER ICDRR ICDRS ICDRT SAR SDA NF2CYC Transfer clock generation circuit Address comparator Interrupt generator Interrupt request Bus state decision circuit Arbitration decision circuit Noise filter Noise filter Output control Output control Transmission/ reception control circuit I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register NF2CYC register [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: NF2CYC: Figure 17.1 Block Diagram of I 2C Bus Interface 3 |
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