SH7261 datasheet(760/1348 Pages) RENESAS

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Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 728 of 1312

REJ09B0320-0200

16.6.6

Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the

SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.

Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in

figure 16.17.

0123456789 10 11 12 13 14 15 012345

0 12345

6 7 8 9 10 11 12 13 14 15

16 clocks

8 clocks

Base clock

Receive data

(RxD)

Start bit

–7.5 clocks

+7.5 clocks

Synchronization

sampling timing

Data sampling

timing

Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.

Equation 1:

M = (0.5 -

) - (L - 0.5) F -

(1 + F)

× 100 %

D - 0.5

Where: M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 16)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute deviation of clock frequency

From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.

Equation 2:

When D = 0.5 and F = 0:

M = (0.5 - 1/(2

× 16)) × 100%

= 46.875%

This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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