SH7261 datasheet(761/1348 Pages) RENESAS

761 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 729 of 1312

REJ09B0320-0200

Section 17 I

2C Bus Interface 3 (IIC3)

The I

2C bus interface 3 conforms to and provides a subset of the Philips I2C (Inter-IC) bus

interface functions. However, the configuration of the registers that control the I

2C bus differs

partly from the Philips register configuration.

17.1

Features

• Selection of I2C format or clocked synchronous serial format

• Continuous transmission/reception

Since the shift register, transmit data register, and receive data register are independent from

each other, the continuous transmission/reception can be performed.

2C bus format:

• Start and stop conditions generated automatically in master mode

• Selection of acknowledge output levels when receiving

• Automatic loading of acknowledge bit when transmitting

• Bit synchronization/wait function

In master mode, the state of SCL is monitored per bit, and the timing is synchronized

automatically. If transmission/reception is not yet possible, set the SCL to low until

preparations are completed.

• Six interrupt sources

Transmit data empty (including slave-address match), transmit end, receive data full (including

slave-address match), arbitration lost, NACK detection, and stop condition detection

• The direct memory access controller (DMAC) can be activated by a transmit-data-empty

request or receive-data-full request to transfer data.

• Direct bus drive

Two pins, SCL0 to SCL2 and SDA0 to SDA2, function as NMOS open-drain outputs when the

bus drive function is selected.

Clocked synchronous serial format:

• Four interrupt sources

Transmit-data-empty, transmit-end, receive-data-full, and overrun error

• The direct memory access controller (DMAC) can be activated by a transmit-data-empty

request or receive-data-full request to transfer data.

SH7261 Datasheet(PDF) 761 Page - Renesas Technology Corp