SH7261 datasheet(771/1348 Pages) RENESAS

771 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 739 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

BCWP

R/W

BC Write Protect

Controls the BC[2:0] modifications. When modifying the

BC[2:0] bits, this bit should be cleared to 0. In clocked

synchronous serial mode, the BC[2:0] bits should not

be modified.

0: When writing, values of the BC[2:0] bits are set.

1: When reading, 1 is always read.

When writing, settings of the BC[2:0] bits are invalid.

Bit Counter

These bits specify the number of bits to be transferred

next. When read, the remaining number of transfer bits

is indicated. With the I

2C bus format, the data is

transferred with one addition acknowledge bit. Should

be made between transfer frames. If these bits are set

to a value other than B'000, the setting should be made

while the SCL pin is low. The value returns to B'000 at

the end of a data transfer, including the acknowledge

bit. These bits are cleared by a power-on reset, in deep

standby mode, software standby mode, or module

standby mode. These bits are also cleared by setting

the IICRST bit of ICCR2 to 1. With the clocked

synchronous serial format, these bits should not be

modified.

2 to 0

BC[2:0]

000

R/W

2C Bus Format

000: 9 bits

001: 2 bits

010: 3 bits

011: 4 bits

100: 5 bits

101: 6 bits

110: 7 bits

111: 8 bits

Clocked Synchronous Serial Format

000: 8 bits

001: 1 bit

010: 2 bits

011: 3 bits

100: 4 bits

101: 5 bits

110: 6 bits

111: 7 bits

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