SH7261 datasheet(780/1348 Pages) RENESAS

780 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 748 of 1312

REJ09B0320-0200

17.4

Operation

The I

2C bus interface 3 can communicate either in I2C bus mode or clocked synchronous serial

mode by setting FS in SAR.

17.4.1

2C Bus Format

Figure 17.3 shows the I

2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame

following a start condition always consists of eight bits.

SLA

DATA

SLA

7n1

DATA

1m1

SLA

1m2

DATA

(a) I2C bus format (FS = 0)

(b) I2C bus format (Start condition retransmission, FS = 0)

n: Transfer bit count (n = 1 to 8)

m: Transfer frame count (m

≥ 1)

n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)

m1 and m2: Transfer frame count (m1 and m2

≥ 1)

Figure 17.3 I

2C Bus Formats

SDA

SCL

SLA

1-7

DATA

Figure 17.4 I

2C Bus Timing

[Legend]

Start condition. The master device drives SDA from high to low while SCL is high.

SLA:

Slave address

Indicates the direction of data transfer: from the slave device to the master device when

R/W is 1, or from the master device to the slave device when R/W is 0.

Acknowledge. The receive device drives SDA to low.

DATA: Transfer data

Stop condition. The master device drives SDA from low to high while SCL is high.

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