SH7261 datasheet(182/1348 Pages) RENESAS

182 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 150 of 1312

REJ09B0320-0200

6.6

Operation

6.6.1

Interrupt Operation Sequence

The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,

following the priority levels set in interrupt priority registers 01, 02, and 05 to 16 (IPR01,

IPR02, and IPR05 to IPR16). Lower priority interrupts are ignored*. If two of these interrupts

have the same priority level or if multiple interrupts occur within a single IPR, the interrupt

with the highest priority is selected, according to the default priority and IPR setting unit

internal priority shown in table 6.4.

3. The priority level of the interrupt selected by the interrupt controller is compared with the

interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt

request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is

ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the

interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU.

4. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes

the instruction to be executed. Instead of executing the decoded instruction, the CPU starts

interrupt exception handling (figure 6.4).

5. The start address of the interrupt exception service routine is fetched from the exception

handling vector table corresponding to the accepted interrupt.

6. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt

is copied to bits I3 to I0 in SR.

7. The program counter (PC) is saved onto the stack.

8. The CPU jumps to the fetched start address of the interrupt exception service routine and starts

executing the program. The jump that occurs is not a delayed branch.

Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the

interrupt source flag, "time from occurrence of interrupt request until interrupt controller

identifies priority, compares it with mask bits in SR, and sends interrupt request signal to

CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually

cancelled. To ensure that an interrupt request that should have been cleared is not

inadvertently accepted again, read the interrupt source flag after it has been cleared, and

then execute an RTE instruction.

* Interrupt requests that are designated as edge-sensing are held pending until the

interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing

the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ

Interrupts.

Interrupts held pending due to edge-sensing are cleared by a power-on reset or in deep

standby mode.

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