SH7261 datasheet(186/1348 Pages) RENESAS

186 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 154 of 1312

REJ09B0320-0200

Number of States

Item

NMI

User Break H-UDI

IRQ, PINT

Peripheral

Module

Remarks

Min.

5 Icyc +

2 Bcyc +

1 Pcyc +

m1 + m2

6 Icyc +

m1 + m2

5 Icyc +

1 Pcyc +

m1 + m2

5 Icyc +

3 Bcyc +

1 Pcyc +

m1 + m2

5 Icyc +

1 Bcyc +

1 Pcyc +

m1 + m2

120-MHz operation*

1*2:

0.067 to 0.142

µs

banking

Max.

6 Icyc +

2 Bcyc +

1 Pcyc +

2 (m1 + m2)

+ m3

7 Icyc +

2 (m1 + m2)

+ m3

6 Icyc +

1 Pcyc +

2 (m1 + m2)

+ m3

6 Icyc +

3 Bcyc +

1 Pcyc +

2 (m1 + m2)

+ m3

6 Icyc +

1 Bcyc +

1 Pcyc +

2 (m1 + m2)

+ m3

120-MHz operation*

1*2:

0.100 to 0.175

µs

Min.



5 Icyc +

1 Pcyc +

m1 + m2

5 Icyc +

3 Bcyc +

1 Pcyc +

m1 + m2

5 Icyc +

1 Bcyc +

1 Pcyc +

m1 + m2

120-MHz operation*

1*2:

0.092 to 0.142

µs

banking

without

bank

overflow

Max.



14 Icyc +

1 Pcyc +

m1 + m2

14 Icyc +

3 Bcyc +

1 Pcyc +

m1 + m2

14 Icyc +

1 Bcyc +

1 Pcyc +

m1 + m2

120-MHz operation*

1*2:

0.167 to 0.217

µs

Min.



5 Icyc +

1 Pcyc +

m1 + m2

5 Icyc +

3 Bcyc +

1 Pcyc +

m1 + m2

5 Icyc +

1 Bcyc +

1 Pcyc +

m1 + m2

120-MHz operation*

1*2:

0.092 to 0.142

µs

Interrupt

response

time

banking

with

bank

overflow

Max.



5 Icyc +

1 Pcyc +

m1 + m2 +

19 (m4)

5 Icyc +

3 Bcyc +

1 Pcyc +

m1 + m2 +

19 (m4)

5 Icyc +

1 Bcyc +

1 Pcyc +

m1 + m2 +

19 (m4)

120-MHz operation*

1*2:

0.245 to 0.300

µs

Notes: m1 to m4 are the number of states needed for the following memory accesses.

m1: Vector address read (longword read)

m2: SR save (longword write)

m3: PC save (longword write)

m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the

stack.

1. In the case of m1 = m2 = m3 = m4 = 1 Icyc.

2. In the case of I

φ:Bφ:Pφ = 120:60:30 [MHz].

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