SH7261 datasheet(187/1348 Pages) RENESAS

187 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 155 of 1312

REJ09B0320-0200

2 Icyc + 3 Bcyc + 1 Pcyc

3 Icyc

3 Icyc + m1 + m2

IRQ

Instruction (instruction replacing

interrupt exception handling)

m1:

m2:

m3:

First instruction in

interrupt service routine

Interrupt acceptance

[Legend]

Vector address read

Saving of SR (stack)

Saving of PC (stack)

Instruction fetch. Instruction is fetched from memory in which program is stored.

Instruction decoding. Fetched instruction is decoded.

Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.

Memory access. Memory data access is performed.

Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted

(No Register Banking)

2 Icyc + 3 Bcyc + 1 Pcyc

1 Icyc + m1 + 2(m2) + m3

3 Icyc + m1

IRQ

[Legend]

m1:

m2:

m3:

Vector address read

Saving of SR (stack)

Saving of PC (stack)

Interrupt acceptance

Multiple interrupt acceptance

First instruction in

interrupt service routine

First instruction in

multiple interrupt service routine

Figure 6.5 Example of Pipeline Operation for Multiple Interrupts

(No Register Banking)

SH7261 Datasheet(PDF) 187 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 187 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL