SH7261 datasheet(188/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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188 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 156 of 1312

REJ09B0320-0200

2 Icyc + 3 Bcyc + 1 Pcyc

3 Icyc

3 Icyc + m1 + m2

IRQ

MMM

[Legend]

m1:

m2:

m3:

Vector address read

Saving of SR (stack)

Saving of PC (stack)

Interrupt acceptance

First instruction in

interrupt service routine

Instruction (instruction replacing

interrupt exception handling)

Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted

(Register Banking without Register Bank Overflow)

2 Icyc + 3 Bcyc + 1 Pcyc

3 Icyc + m1 + m2

m1 m2 m3

9 Icyc

IRQ

RESBANK instruction

EEEEEEEE

[Legend]

m1:

m2:

m3:

Vector address read

Saving of SR (stack)

Saving of PC (stack)

Interrupt acceptance

First instruction in

interrupt service routine

Instruction (instruction replacing

interrupt exception handling)

Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK

Instruction Execution (Register Banking without Register Bank Overflow)

SH7261 Datasheet(PDF) 188 Page - Renesas Technology Corp

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