SH7261 datasheet(192/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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192 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 160 of 1312

REJ09B0320-0200

Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place

between the start of interrupt exception handling and the start of fetching the first instruction in the

exception service routine.

2 Icyc + 3 Bcyc + 1 Pcyc

3 Icyc

3 Icyc + m1 + m2

IRQ

(1) VTO, PR, GBR, MACL

(2) R12, R13, R14, MACH

(3) R8, R9, R10, R11

(4) R4, R5, R6, R7

(5) R0, R1, R2, R3

Overrun fetch

Saved to bank

MMM

[Legend]

m1:

m2:

m3:

Vector address read

Saving of SR (stack)

Saving of PC (stack)

First instruction in

interrupt service routine

Instruction (instruction replacing

interrupt exception handling)

Figure 6.12 Bank Save Timing

(2)

Restoration from Bank

The RESBANK (restore from register bank) instruction is used to restore data saved in a register

bank. After restoring data from the register banks with the RESBANK instruction at the end of the

interrupt service routine, execute the RTE instruction to return from exception handling.

SH7261 Datasheet(PDF) 192 Page - Renesas Technology Corp