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SH7261 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 1348 page  Section 7 User Break Controller (UBC) Rev. 2.00 Sep. 07, 2007 Page 183 of 1312 REJ09B0320-0200 (3) Break Condition Specified for I Bus Data Access Cycle (Example 3-1) • Register specifications BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0094, BAR_1= H'00055555, BAMR_1 = H'00000000, BBR_1 = H'11A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F, BRCR = H'00000000 <Channel 0> Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition) <Channel 1> Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus/data access/write/byte On channel 0, the setting of I bus/instruction fetch is ignored. On channel 1, a user break occurs when the CPU writes byte data H'7x in address H'00055555 on the I bus. |
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