SH7261 datasheet(212/1348 Pages) RENESAS

212 / 1348 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 180 of 1312

REJ09B0320-0200

7.4.4

Value of Saved Program Counter

When a user break interrupt request is received, the address of the instruction from where

execution is to be resumed is saved to the stack, and the exception handling state is entered. If the

C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the

break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access

cycle is specified as a break condition, the instruction at which the break should occur cannot be

uniquely determined.

1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break

condition:

The address of the instruction that matched the break condition is saved to the stack. The

instruction that matched the condition is not executed, and the break occurs before it.

However, when a delay slot instruction matches the condition, the instruction is executed, and

the branch destination address is saved to the stack.

2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break

condition:

The address of the instruction following the instruction that matched the break condition is

saved to the stack. The instruction that matches the condition is executed, and the break occurs

before the next instruction is executed. However, when a delayed branch instruction or delay

slot matches the condition, the instruction is executed, and the branch destination address is

saved to the stack.

3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition:

The address after executing several instructions of the instruction that matched the break

condition is saved to the stack.

SH7261 Datasheet(PDF) 212 Page - Renesas Technology Corp