SH7261 datasheet(213/1348 Pages) RENESAS

213 / 1348 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 181 of 1312

REJ09B0320-0200

7.4.5

Usage Examples

(1)

Break Condition Specified for C Bus Instruction Fetch Cycle

(Example 1-1)

• Register specifications

BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010,

BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000,

BRCR = H'00000020

Address:

H'00000404, Address mask: H'00000000

Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

Address:

H'00008010, Address mask: H'00000006

Data:

H'00000000, Data mask: H'00000000

Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

A user break occurs after an instruction of address H'00000404 is executed or before

instructions of addresses H'00008010 to H'00008016 are executed.

(Example 1-2)

• Register specifications

BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415,

BAMR_1 = H'00000000, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000,

BRCR = H'00000000

Address:

H'00027128, Address mask: H'00000000

Bus cycle: C bus/instruction fetch (before instruction execution)/write/word

Address:

H'00031415, Address mask: H'00000000

Data:

H'00000000, Data mask: H'00000000

Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

On channel 0, a user break does not occur since instruction fetch is not a write cycle. On

channel 1, a user break does not occur since instruction fetch is performed for an even address.

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