SH7261 datasheet(209/1348 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 177 of 1312

REJ09B0320-0200

7.4

Operation

7.4.1

Flow of the User Break Operation

The flow from setting of break conditions to user break exception handling is described below:

1. The break address is set in the break address register (BAR). The masked address bits are set in

the break address mask register (BAMR). The break data is set in the break data register

(BDR). The masked data bits are set in the break data mask register (BDMR). The bus break

conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C

bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each

set. No user break will be generated if even one of these groups is set to 00. The relevant break

control conditions are set in the bits of the break control register (BRCR). Make sure to set all

registers related to breaks before setting BBR, and branch after reading from the last written

destination.

2. In the case where the break conditions are satisfied and the user break interrupt request is

enabled, the UBC sends a user break request to the INTC, sets the C bus condition match flag

(SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel, and outputs a

pulse to the

UBCTRG pin with the width set by the CKS[1:0] bits. Setting the UBID bit in

BBR to 1 enables external monitoring of the trigger output without requesting user break

interrupts.

3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the

user break interrupt has a priority level of 15, it is accepted when the priority level set in the

interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits

are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are

checked, and condition match flags are set if the conditions match. For details on ascertaining

the priority, see section 6, Interrupt Controller (INTC).

4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been

satisfied. Clear the condition match flags during the user break interrupt exception processing

routine. The interrupt occurs again if this operation is not performed.

5. There is a chance that the break set in channel 0 and the break set in channel 1 occur around

the same time. In this case, there will be only one break request to the INTC, but these two

break channel match flags may both be set.

6. When selecting the I bus as the break condition, note as follows:

 Whether or not the access the CPU issued on the C bus is issued on the I bus depends on

the setting of the cache. As regard to the I bus operation that depends on cache conditions,

see table 8.8 in section 8, Cache.

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