SH7261 datasheet(207/1348 Pages) RENESAS

207 / 1348 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 175 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

SCMFC0

R/W

C Bus Cycle Condition Match Flag 0

When the C bus cycle condition in the break conditions

set for channel 0 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The C bus cycle condition for channel 0 does not

match

1: The C bus cycle condition for channel 0 matches

SCMFC1

R/W

C Bus Cycle Condition Match Flag 1

When the C bus cycle condition in the break conditions

set for channel 1 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The C bus cycle condition for channel 1 does not

match

1: The C bus cycle condition for channel 1 matches

SCMFD0

R/W

I Bus Cycle Condition Match Flag 0

When the I bus cycle condition in the break conditions

set for channel 0 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The I bus cycle condition for channel 0 does not

match

1: The I bus cycle condition for channel 0 matches

SCMFD1

R/W

I Bus Cycle Condition Match Flag 1

When the I bus cycle condition in the break conditions

set for channel 1 is satisfied, this flag is set to 1. In

order to clear this flag, write 0 to this bit.

0: The I bus cycle condition for channel 1 does not

match

1: The I bus cycle condition for channel 1 matches

11 to 7



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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