SH7261 datasheet(205/1348 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 173 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

7, 6

CD[1:0]

R/W

C Bus Cycle/I Bus Cycle Select

Select the C bus cycle or I bus cycle as the bus cycle

of the break condition.

00: Condition comparison is not performed

01: Break condition is the C bus (F bus or M bus) cycle

10: Break condition is the I bus cycle

11: Break condition is the C bus (F bus or M bus) cycle

5, 4

ID[1:0]

R/W

Instruction Fetch/Data Access Select

Select the instruction fetch cycle or data access cycle

as the bus cycle of the break condition. If the

instruction fetch cycle is selected, select the C bus

cycle.

00: Condition comparison is not performed

01: Break condition is the instruction fetch cycle

10: Break condition is the data access cycle

11: Break condition is the instruction fetch cycle or

data access cycle

3, 2

RW[1:0]

R/W

Read/Write Select

Select the read cycle or write cycle as the bus cycle of

the break condition.

00: Condition comparison is not performed

01: Break condition is the read cycle

10: Break condition is the write cycle

11: Break condition is the read cycle or write cycle

1, 0

SZ[1:0]

R/W

Operand Size Select

Select the operand size of the bus cycle for the break

condition.

00: Break condition does not include operand size

01: Break condition is byte access

10: Break condition is word access

11: Break condition is longword access

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