SH7261 datasheet(202/1348 Pages) RENESAS

202 / 1348 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 170 of 1312

REJ09B0320-0200

7.3.3

Break Data Register (BDR)

BDR is a 32-bit readable/writable register. The control bits CD[1:0] in the break bus cycle register

(BBR) select one of the two data buses for a break condition. BDR is initialized to H'00000000 by

a power-on reset or in deep standby, but retains its previous value by a manual reset or in software

standby mode or sleep mode.

987654321

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16

BD15 BD14 BD13 BD12 BD11 BD10 BD9

BD8

BD7

BD6

BD5

BD4

BD3

BD2

BD1

BD0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BD31 to BD0 All 0

R/W

Break Data Bits

Store data which specifies a break condition.

If the I bus is selected in BBR, specify the break data

on IDB in bits BD31 to BD0.

If the C bus is selected in BBR, specify the break data

on MDB in bits BD31 to BD0.

Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.

2. When the byte size is selected as a break condition, the same byte data must be set in

bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the

word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0.

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