SH7261 datasheet(200/1348 Pages) RENESAS

200 / 1348 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 168 of 1312

REJ09B0320-0200

7.3.1

Break Address Register (BAR)

BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in

each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the

three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset or

in deep standby, but retains its previous value by a manual reset or in software standby mode or

sleep mode.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16

BA15 BA14 BA13 BA12 BA11 BA10

BA9

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BA31 to BA0 All 0

R/W

Break Address

Store an address on the CPU address bus (FAB or

MAB) or IAB specifying break conditions.

When the C bus and instruction fetch cycle are

selected by BBR, specify an FAB address in bits BA31

to BA0.

When the C bus and data access cycle are selected by

BBR, specify an MAB address in bits BA31 to BA0.

Note:

When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.

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