SH7261 datasheet(199/1348 Pages) RENESAS

199 / 1348 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 167 of 1312

REJ09B0320-0200

7.2

Input/Output Pin

Table 7.1 shows the pin configuration of the UBC.

Table 7.1

Pin Configuration

Pin Name

Symbol

I/O

Function

UBC trigger

UBCTRG

Output

Indicates that a setting condition is satisfied on

either channel 0 or 1 of the UBC.

7.3

The UBC has the following registers.

Table 7.2

Channel

Abbrevia-

tion

R/W

Initial Value

Address

Access

Size

Break address register_0

BAR_0

R/W

H'00000000

H'FFFC0400

Break address mask register_0

BAMR_0

R/W

H'00000000

H'FFFC0404

Break bus cycle register_0

BBR_0

R/W

H'0000

H'FFFC04A0

Break data register_0

BDR_0

R/W

H'00000000

H'FFFC0408

Break data mask register_0

BDMR_0

R/W

H'00000000

H'FFFC040C 32

Break address register_1

BAR_1

R/W

H'00000000

H'FFFC0410

Break address mask register_1

BAMR_1

R/W

H'00000000

H'FFFC0414

Break bus cycle register_1

BBR_1

R/W

H'0000

H'FFFC04B0

Break data register_1

BDR_1

R/W

H'00000000

H'FFFC0418

Break data mask register_1

BDMR_1

R/W

H'00000000

H'FFFC041C 32

Common

Break control register

BRCR

R/W

H'00000000

H'FFFC04C0 32

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