SH7261 datasheet(206/1348 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 174 of 1312

REJ09B0320-0200

7.3.6

Break Control Register (BRCR)

BRCR sets the following conditions:

1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle

is set before or after instruction execution.

2. Specifies the pulse width of the

UBCTRG output when a break condition is satisfied.

BRCR is a 32-bit readable/writable register that has break condition match flags and bits for

setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid

(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag

bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on

reset and in deep standby, but retains its previous value by a manual reset or in software standby

mode or sleep mode.

0000000000000000

RRRRRRRRRRRRRR

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:





CKS[1:0]

SCMFC

SCMFD

PCB1 PCB0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 18



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

17, 16

CKS[1:0]

R/W

Clock Select

Specifies the pulse width output to the

UBCTRG pin

when a break condition is satisfied.

00: Pulse width of

UBCTRG is one bus clock cycle

01: Pulse width of

UBCTRG is two bus clock cycles

10: Pulse width of

UBCTRG is four bus clock cycles

11: Pulse width of

UBCTRG is eight bus clock cycles

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