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SH7261 Datasheet(PDF) 208 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 208 Page - Renesas Technology Corp |
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208 / 1348 page ![]() Section 7 User Break Controller (UBC) Rev. 2.00 Sep. 07, 2007 Page 176 of 1312 REJ09B0320-0200 Bit Bit Name Initial Value R/W Description 6 PCB1 0 R/W PC Break Select 1 Selects the break timing of the instruction fetch cycle for channel 1 as before or after instruction execution. 0: PC break of channel 1 is generated before instruction execution 1: PC break of channel 1 is generated after instruction execution 5 PCB0 0 R/W PC Break Select 0 Selects the break timing of the instruction fetch cycle for channel 0 as before or after instruction execution. 0: PC break of channel 0 is generated before instruction execution 1: PC break of channel 0 is generated after instruction execution 4 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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