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SH7261 Datasheet(PDF) 319 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 319 Page - Renesas Technology Corp |
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319 / 1348 page  Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 287 of 1312 REJ09B0320-0200 (c) Example of SDRAM Connection Figures 9.42 and 9.43 show examples of the connection of SDRAM with this LSI. A16 A15 A14 A13 to A2 A1, A0 SDCKE SDCLK SDCS SDRAS SDCAS SDWE D13 to D16 DQM3 DQM2 D15 to D0 DQM1 DQM0 64 M SDRAM (1 M × 16 bits × 4 banks) A13 (BA1) A12 (BA0) A11 to A0 CKE CLK CS RAS CAS WE I/O15 to I/O0 DQMU DQML A13 (BA1) A12 (BA0) A11 to A0 CKE CLK CS RAS CAS WE I/O15 to I/O0 DQMU DQML This LSI Not in use Not in use Figure 9.42 Example of Connecting a 32-Bit Data-Width SDRAM |
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