SH7261 datasheet(323/1348 Pages) RENESAS

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Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 291 of 1312

REJ09B0320-0200

Section 10 Bus Monitor

The bus monitor is a module that monitors bus errors on each bus. When an illegal address access

or a bus timeout is detected, a bus error interrupt is generated and an access canceling signal is

output for the bus timeout. (The bus timeout function is used for debugging.)

Figure 10.1 shows a block diagram of the bus monitor.

Bus monitor

Bus monitor enable register

Bus monitor status register 1

SH2A

CPU core

Bus error signal

Peripheral

bus

Bus monitor status register 2

Bus error control register

Figure 10.1 Block Diagram of Bus Monitor

10.1

The bus monitor has the following registers.

All registers are initialized by a power-on reset or in deep standby mode.

Table 10.1

Abbreviation

R/W

Initial Value

Address

Access

Size

Bus monitor enable register

SYCBEEN

R/W

H'00

H'FF400000

8, 16, 32

Bus monitor status register 1

SYCBESTS1

R/W

H'00

H'FF400004

8, 16, 32

Bus monitor status register 2

SYCBESTS2

R/W

H'00

H'FF400008

8, 16, 32

Bus error control register

SYCBESW

R/W

H'00

H'FF40000C

8, 16, 32

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