SH7261 datasheet(326/1348 Pages) RENESAS

326 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 294 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

9, 8

PMST[1:0]

Bus Master

These bits indicate the bus master that accessed

peripheral bus (1) when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)



Reserved

This bit is always read as 0. The write value should

always be 0.

CTO

Timeout

This bit indicates that a timeout occurred on peripheral

bus (3) when the first bus error occurred.

0: Timeout not generated

1: Timeout generated

CER

Illegal Address Access

This bit indicates that an illegal address access was

made on peripheral bus (3) when the first bus error

occurred.

0: Illegal address access not made

1: Illegal address access made

4 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

CMST[1:0]

Bus Master

These bits indicate the bus master that accessed

peripheral bus (3) when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)

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