SH7261 datasheet(327/1348 Pages) RENESAS

327 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 295 of 1312

REJ09B0320-0200

Table 10.2

Bus Space and Slave Bus

Address

Bus Space

Slave Bus

H'0000 0000 to H'4FFF FFFF

External bus space

External bus

H'5000 0000 to H'E7FF FFFF

Reserved

(Others*

H'E800 0000 to H'E800 FFFF

On-chip peripheral module (3)

Peripheral bus (3)

H'E801 0000 to H'EFFF FFFF

Reserved

(Others*

H'F000 0000 to H'F1FF FFFF

Address array space in cache

*2

H'F200 0000 to H'F5FF FFFF

Reserved

*2

H'F600 0000 to H'FF3F FFFF

Reserved

(Others*

H'FF40 0000 to H'FF5F FFFF

On-chip peripheral module (1)

Peripheral bus (1)

H'FF60 0000 to H'FFF7 FFFF

Reserved

(Others*

H'FFF8 0000 to H'FFF8 7FFF

On-chip RAM

*2

H'FFF8 8000 to H'FFFB FFFF

Reserved

*2

H'FFFC 0000 to H'FFFF FFFF

On-chip peripheral module (2)

Peripheral bus (2)

Notes: 1. This means bus spaces in the slave bus space other than those for the external bus

and peripheral buses (1), (2), and (3).

2. An illegal address access error does not occur.

10.1.3

Bus Monitor Status Register 2 (SYCBESTS2)

SYCBESTS2 indicates the status of slave buses (external bus/peripheral bus (2)/others) regarding

whether a timeout occurred, whether an illegal address access was made, or which bus master

accessed the slave bus.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

—

———

————————

ETO

EER

EMST[1:0]

—

OER

—

OMST[1:0]

—

SHER

—

SHMST[1:0]

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