SH7261 datasheet(329/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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329 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 297 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

12 to 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

9, 8

OMST[1:0]

R/W

Bus Master

These bits indicate the bus master that accessed other

buses when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)

7, 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SHER

Illegal Address Access

This bit indicates that an illegal address access was

made on peripheral bus (2) when the first bus error

occurred.

0: Illegal address access not made

1: Illegal address access made

4 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

SHMST

[1:0]

Bus Master

These bits indicate the bus master that accessed

peripheral bus (2) when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)

SH7261 Datasheet(PDF) 329 Page - Renesas Technology Corp

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