SH7261 datasheet(328/1348 Pages) RENESAS

328 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 296 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

ETO

Timeout

This bit indicates that a timeout occurred on the

external bus when the first bus error occurred.

0: Timeout not generated

1: Timeout generated

EER

Illegal Address Access

This bit indicates that an illegal address access was

made on the external bus when the first bus error

occurred.

0: Illegal address access not made

1: Illegal address access made

28 to 26



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

25, 24

EMST[1:0]

Bus Master

These bits indicate the bus master that accessed the

external bus when the first bus error occurred.

00: CPU

01: DMAC (destination side)

10: Setting prohibited

11: DMAC (source side)

23 to 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

OER

Illegal Address Access

These bits indicate the bus master that accessed other

buses when the first bus error occurred.

0: Illegal address access not made

1: Illegal address access made

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