SH7261 datasheet(324/1348 Pages) RENESAS

324 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 292 of 1312

REJ09B0320-0200

10.1.1

Bus Monitor Enable Register (SYCBEEN)

SYCBEEN clears the bus monitor status register and controls the detection function.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

R/W

RRRRRRRRRRRR

R/W

0000000000000000

RRRRRRRRRRRRRRRR

STS

CLR

—

TOEN IGAEN

—

——

—————

Bit

Bit Name

Initial

Value

R/W

Description

STSCLR

R/W

Status Clear

Writing 1 to this bit clears the bus monitor status

0: Invalid

1: Bus monitor status register cleared

30 to 19



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TOEN

R/W

Timeout Detection Enable

This bit enables or disables the function that detects a

bus timeout on each bus.

0: Bus timeout detection function disabled

1: Bus timeout detection function enabled

IGAEN

R/W

Illegal Address Access Detection Enable

This bit enables or disables the function that detects an

illegal address access on each bus.

0: Illegal address access detection function disabled

1: Illegal address access detection function enabled

16 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

When a bus access is performed with the detection function disabled (TOEN

= 0), the bus

may freeze.

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