SH7261 datasheet(325/1348 Pages) RENESAS

325 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 293 of 1312

REJ09B0320-0200

10.1.2

Bus Monitor Status Register 1 (SYCBESTS1)

SYCBESTS1 indicates the status of slave buses (peripheral bus (1)/peripheral bus (3)) regarding

whether a timeout occurred, whether an illegal address access was made, or which bus master

accessed the slave bus. Table 10.2 shows the correspondence between the bus spaces and the slave

buses.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

RRRRRRRRRRRRRRR

0000000000000000

————————————————

—

PTO

PER

—

PMST[1:0]

—

CTO

CER

—

CMST[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PTO

Timeout

This bit indicates that a timeout occurred on peripheral

bus (1) when the first bus error occurred.

0: Timeout not generated

1: Timeout generated

PER

Illegal Address Access

This bit indicates that an illegal address access was

made on peripheral bus (1) when the first bus error

occurred.

0: Illegal address access not made

1: Illegal address access made

12 to 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7261 Datasheet(PDF) 325 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 325 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL