SH7261 datasheet(330/1348 Pages) RENESAS

330 / 1348 page

Section 10 Bus Monitor

Rev. 2.00 Sep. 07, 2007 Page 298 of 1312

REJ09B0320-0200

10.1.4

Bus Error Control Register (SYCBESW)

SYCBESW controls the notification of various types of bus errors to the CPU.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000

R/W

RRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRRR

CPEN

—

——————————

————————————————

Bit

Bit Name

Initial

Value

R/W

Description

00CPEN

R/W

Bus Error Control (CPU

→ CPU)

This bit controls notification to the CPU when a bus

error is caused by the CPU.

0: Not notified

1: Notified

01CPEN

R/W

Bus Error Control (DMAC Destination Side

→ CPU)

This bit controls notification to the CPU when a bus

error is caused by the DMAC destination side.

0: Not notified

1: Notified



Reserved

This bit is always read as 0. The write value should

always be 0.

11CPEN

R/W

Bus Error Control (DMAC Source Side

→ CPU)

This bit controls notification to the CPU when a bus

error is caused by the DMAC source side.

0: Not notified

1: Notified

27 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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