HD64F36074G datasheet(85/564 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 Sep. 10, 2007 Page 53 of 528

REJ09B0216-0300

3.2.6

Interrupt Flag Register 2 (IRR2)

IRR2 is a status flag register for timer B1 overflow interrupts.

Bit

Bit Name

Initial

Value

R/W

Description

7, 6



All 0



Reserved

These bits are always read as 0.

IRRTB1

R/W

Timer B1 Interrupt Request flag

[Setting condition]

When the timer B1 counter value overflows

[Clearing condition]

When IRRTB1 is cleared by writing 0

4 to 0



All 1



Reserved

These bits are always read as 1.

3.2.7

Wakeup Interrupt Flag Register (IWPR)

IWPR is a status flag register for

WKP5 to WKP0 interrupt requests.

Bit

Bit Name

Initial

Value

R/W

Description

7, 6



All 1



Reserved

These bits are always read as 1.

IWPF5

R/W

WKP5 Interrupt Request Flag

[Setting condition]

When

WKP5 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF5 is cleared by writing 0.

IWPF4

R/W

WKP4 Interrupt Request Flag

[Setting condition]

When

WKP4 pin is designated for interrupt input and the

designated signal edge is detected.

[Clearing condition]

When IWPF4 is cleared by writing 0.

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