HD64F36074G datasheet(10/564 Pages) RENESAS

10 / 564 page

Rev. 3.00 Sep. 10, 2007 Page x of xxxii

3.2.4

Interrupt Enable Register 2 (IENR2) .................................................................. 51

3.2.5

Interrupt Flag Register 1 (IRR1)......................................................................... 51

3.2.6

Interrupt Flag Register 2 (IRR2)......................................................................... 53

3.2.7

Wakeup Interrupt Flag Register (IWPR) ............................................................ 53

3.3

Reset Exception Handling .................................................................................................. 55

3.4

Interrupt Exception Handling ............................................................................................. 56

3.4.1

External Interrupts .............................................................................................. 56

3.4.2

Internal Interrupts ............................................................................................... 58

3.4.3

Interrupt Handling Sequence .............................................................................. 58

3.4.4

Interrupt Response Time..................................................................................... 60

3.5

Usage Notes ........................................................................................................................ 62

3.5.1

Interrupts after Reset........................................................................................... 62

3.5.2

Notes on Stack Area Use .................................................................................... 62

3.5.3

Notes on Rewriting Port Mode Registers ........................................................... 62

Section 4 Address Break ....................................................................................... 63

4.1

Register Descriptions .......................................................................................................... 64

4.1.1

Address Break Control Register (ABRKCR) ..................................................... 64

4.1.2

Address Break Status Register (ABRKSR) ........................................................ 67

4.1.3

Break Address Registers (BARE, BARH, BARL) ............................................. 67

4.1.4

Break Data Registers (BDRH, BDRL) ............................................................... 67

4.2

Operation ............................................................................................................................ 68

Section 5 Clock Pulse Generator ........................................................................... 71

5.1

Features............................................................................................................................... 72

5.2

Register Descriptions .......................................................................................................... 72

5.2.1

RC Control Register (RCCR) ............................................................................. 73

5.2.2

RC Trimming Data Protect Register (RCTRMDPR).......................................... 74

5.2.3

RC Trimming Data Register (RCTRMDR) ........................................................ 75

5.2.4

Clock Control/Status Register (CKCSR) ............................................................ 76

5.3

System Clock Select Operation .......................................................................................... 79

5.3.1

Clock Control Operation..................................................................................... 79

5.3.2

Clock Switching Timing ..................................................................................... 83

5.4

Trimming of On-Chip Oscillator Frequency ...................................................................... 86

5.5

External Oscillators............................................................................................................. 88

5.5.1

Connecting Crystal Resonator ............................................................................ 88

5.5.2

Connecting Ceramic Resonator .......................................................................... 89

5.5.3

Inputting External Clock..................................................................................... 89

5.6

Subclock Oscillator.............................................................................................................90

5.6.1

Connecting 32.768-kHz Crystal Resonator......................................................... 90

HD64F36074G Datasheet(PDF) 10 Page - Renesas Technology Corp

HD64F36074G Datasheet(HTML) 10 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL