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HD64F36074G Datasheet(PDF) 98 Page - Renesas Technology Corp |
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HD64F36074G Datasheet(HTML) 98 Page - Renesas Technology Corp |
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98 / 564 page  Section 4 Address Break Rev. 3.00 Sep. 10, 2007 Page 66 of 528 REJ09B0216-0300 When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 21.1, Register Addresses (Address Order). Table 4.1 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits I/O register with 8-bit data bus width Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits I/O register with 16-bit data bus width Upper 8 bits Lower 8 bits |
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