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HD64F36074G Datasheet(PDF) 27 Page - Renesas Technology Corp |
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HD64F36074G Datasheet(HTML) 27 Page - Renesas Technology Corp |
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27 / 564 page  Rev. 3.00 Sep. 10, 2007 Page xxvii of xxxii Figure 18.5 A/D Conversion Accuracy Definitions (2) .............................................................. 377 Figure 18.6 Analog Input Circuit Example................................................................................. 378 Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Figure 19.1 Block Diagram around BGR ................................................................................... 380 Figure 19.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit..................................................................................................... 381 Figure 19.3 Operational Timing of Power-On Reset Circuit ...................................................... 387 Figure 19.4 Operating Timing of LVDR Circuit ........................................................................ 388 Figure 19.5 Operational Timing of LVDI Circuit....................................................................... 389 Figure 19.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins) ......................... 391 Figure 19.7 Timing of Setting Bits in Reset Source Decision Register ...................................... 392 Section 20 Power Supply Circuit Figure 20.1 Power Supply Connection of 5.0-V-Specification Microcontrollers....................... 393 Figure 20.2 Power Supply Connection of 3.3-V-Specification Microcontrollers....................... 394 Section 22 Electrical Characteristics Figure 22.1 System Clock Input Timing..................................................................................... 455 Figure 22.2 RES Low Width Timing..........................................................................................455 Figure 22.3 Input Timing............................................................................................................ 455 Figure 22.4 I2C Bus Interface Input/Output Timing ................................................................... 456 Figure 22.5 SCK3 Input Clock Timing....................................................................................... 456 Figure 22.6 SCI Input/Output Timing in Clock Synchronous Mode.......................................... 457 Figure 22.7 Output Load Circuit................................................................................................. 458 Appendix Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 489 Figure B.2 Port 1 Block Diagram (P14, P16) ............................................................................. 490 Figure B.3 Port 1 Block Diagram (P15) ..................................................................................... 491 Figure B.4 Port 1 Block Diagram (P12) ..................................................................................... 492 Figure B.5 Port 2 Block Diagram (P11) ..................................................................................... 493 Figure B.6 Port 1 Block Diagram (P10) ..................................................................................... 494 Figure B.7 Port 2 Block Diagram (P24, P23) ............................................................................. 495 Figure B.8 Port 2 Block Diagram (P22) ..................................................................................... 496 Figure B.9 Port 2 Block Diagram (P21) ..................................................................................... 497 Figure B.10 Port 2 Block Diagram (P20) ................................................................................... 498 Figure B.11 Port 3 Block Diagram (P37 to P30) ........................................................................ 499 Figure B.12 Port 5 Block Diagram (P57, P56) ........................................................................... 500 Figure B.13 Port 5 Block Diagram (P55) ................................................................................... 501 Figure B.14 Port 5 Block Diagram (P54 to P50) ........................................................................ 502 |
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