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AFE5804 Datasheet(PDF) 43 Page - Texas Instruments |
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AFE5804 Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 60 page ![]() BIT CLOCK PROGRAMMABILITY FCLKP LCLKP OUTP PHASE_DDR<1:0>= '00' PHASE_DDR<1:0>= '01' PHASE_DDR<1:0>= '10' PHASE_DDR<1:0>= '11' FCLKP LCLKP OUTP FCLKP LCLKP OUTP FCLKP LCLKP OUTP FCLKP LCLKP OUTP AFE5804 www.ti.com ................................................................................................................................................ SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008 The output interface of the AFE5804 is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. Figure 92 shows this default phase. Figure 92. LCLK Default Phase The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>. Figure 93 shows the LCLK phase modes. Figure 93. LCLK Phase Programmability Modes Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Link(s): AFE5804 |
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