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SH7018 Datasheet(PDF) 76 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 76 Page - Renesas Technology Corp |
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76 / 431 page ![]() 60 6.1.2 Block Diagram Figure 6.1 is a block diagram of the INTC. CPU SR Interrupt request Com- parator Priority ranking judg- ment CPU Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) ISR ICR IPR IPRA to IPRH Module bus Bus interface I3 I2 I1 I0 INTC NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7 MTU CMT SCI1 A/D WDT (Interrupt request) TIM2 MTU: CMT: SCI1: A/D: WDT: TIM2: ICR: ISR: IPRA to IPRH: SR: Interrupt control register IRQ ststus register Interrupt priority level setting registers A to H Status register Multifunction timer pulse unit Compare match timer Serial communication interface A/D converter Watchdog Timer 8-bit timer Figure 6.1 INTC Block Diagram |
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