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SH7018 Datasheet(PDF) 91 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 91 Page - Renesas Technology Corp |
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91 / 431 page  75 Section 7 Bus State Controller (BSC) 7.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the LSI without external circuitry. 7.1.1 Features • Address space is divided into four spaces A maximum linear 2 Mbytes for address space CS0 A maximum linear 4 Mbytes for each of address spaces CS1 to CS3 8-bit bus width Wait states can be inserted by software for each space (0 to 3 waits) In external memory space access, wait states can be inserted by the WAIT pin Outputs control signals for each space according to the type of memory connected • RAM interface On-chip RAM access of 32 bits in 1 state |
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