SH7018 datasheet(93/431 Pages) RENESAS

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7.1.3

Pin Configuration

Table 7.1 shows the bus state controller pin configuration.

Table 7.1

Pin Configuration

Pin Name

I/O

Function

A21 to A0

Output

Address output

D7 to D0

I/O

8-bit data bus

CS0 to CS3

Output

Chip select

Output

Strobe that indicates a read cycle for ordinary space/multiplex I/O

WRL

Output

Strobe that indicates a write cycle

WAIT

Input

Wait state request signal

7.1.4

The bus state controller has three registers. The functions of these registers include control of wait

states and interfaces with memories such as ROM and SRAM. The registers are summarized in

table 7.2.

Both registers are 16 bits in size, and are initialized by a power-on reset.

Table 7.2

Name

Abbr.

R/W

Initial Value Address

Access Size

Bus control register 1

BCR1

R/W

H'200F

H'FFFF8620 8, 16

Bus control register 2

BCR2

R/W

H'FFFF

H'FFFF8622 8, 16

Wait state control register 1

WCR1

R/W

H'FFFF

H'FFFF8624 8, 16

SH7018 Datasheet(PDF) 93 Page - Renesas Technology Corp

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