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SH7052 Datasheet(PDF) 422 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 422 Page - Renesas Technology Corp

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Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow
occurs in the T2 state of a down-counter start register (DSTR) “1” write cycle by the CPU,
clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1.
The timing in this case is shown in figure 10.73.
Pø
T1
DSTR address
STR write cycle
1 written
to DSTR
Internal write signal
Underflow signal
Address
Down-count start
register
T2
DCNT
0000
0000
0001
Figure 10.73 Contention between DSTR Bit Setting by CPU and Clearing by Underflow



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