SH7052 datasheet(423/919 Pages) RENESAS

423 / 919 page

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Timing of Prescaler Register (PSCR), Timer Control Register (TCR), and Timer Mode

and timer mode register (TMDR) should be made before the counter is started. Operation is not

guaranteed if these registers are modified while the counter is running.

Also, the counter must not be started until Pø has been input 32 times after setting PSCR1 to

PSCR4.

Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the

CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is

written without first reading the flag.

Setting H'0000 in Free-Running Counters 6A to 6D, 7A to 7D (TCNT6A to TCNT6D,

TCNT7A to TCNT7D): If H'0000 is written to a channel 6 and 7 free-running counter (TCNT6A

to TCNT6D, TCNT7A to TCNT7D), and the counter is started, the interval up to the first

compare-match with the cycle register (CYLR) and duty register (DTR) will be a maximum of one

TCNT input clock cycle longer than the set value. With subsequent compare-matches, the correct

waveform will be output for the CYLR and DTR values.

(TSTR) value is set to 0 during counter operation, only incrementing of the corresponding free-

running counter (TCNT) is stopped, and neither the free-running counter (TCNT) nor any other

ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will

continue to be output.

TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in free-

running counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register

(ITVRR) when that TCNT0 bit is 0, TCNT0 bit 6, 7, 8, 9, 10, 11, 12, or 13 will be detected as

having changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will

be started. While the count is halted with the STR0 bit cleared to 0 in timer start register 1

(TSTR1), the bit transition from 0 to 1 will still be detected.

Automatic TSR Clearing by DMAC Activation by the ATU: Automatic clearing of TSR is

performed after completion of the transfer when the DMAC is in burst mode, and each time the

DMAC returns the bus in cycle steal mode.

Interrupt Status Flag Setting/Resetting: With TSR, a 0 write to a bit is possible even if

overlapping events occur for the same bit before writing 0 after reading 1 to clear that bit. (The

duplicate events are not accepted.)

SH7052 Datasheet(PDF) 423 Page - Renesas Technology Corp