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SH7052 Datasheet(PDF) 446 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 446 Page - Renesas Technology Corp |
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446 / 919 page ![]() 420 H'A5 H'FFFFEC12 Address: Writing 0 to the WOVF bit 15 8 7 0 H'00 H'5A H'FFFFEC12 Address: Writing to the RSTE and RSTS bits 15 8 7 0 Write data Figure 12.3 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFEC10 for TCSR, H'FFFFEC11 for TCNT, and H'FFFFEC13 for RSTCSR. 12.3 Operation 12.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/ IT and TME bits of TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally (figure 12.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 φ clock cycles. If the RSTE bit in the reset control/status register (RSTCSR) is set to 1, a signal that resets the chip internally will be generated at the same time as the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following are not initialized by a WDT reset signal: • PFC (pin function controller) registers • I/O port registers These registers are initialized only by an external power-on reset. |
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